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  • Ing-Chao Lin

    Ing-Chao LinProfessor

    Contact Info.

    Department: dept. CSIE / inst. CSIE / AI Program

    Tel: 06-2757575 ext 62553

    E-mail: iclin@mail.ncku.edu.tw

    Lab: Computer Architecture and IC Design Lab (CAID) (65A02, 10F, CSIE new building)

    Personal Website: http://caid.csie.ncku.edu.tw/prof.php
    Research Interests

    AI Chip and AI Computing Platform、Reliable Energy-Efficient Computer Architecture、Electronic Design Automation、Digital Integrated Circuits/System-on-Chip Design 、Memory Architecture and System、Heterogeneous Computing System and Architecture、In-Memory Computing

    School Record

    United States \ The Pennsylvania State University \ Computer Science and Engineeri \ Ph.D(2002 ~ 2007)

    Taiwan \ National Taiwan University \ Computer Science and Informati \ M.S.(1999 ~ 2001)

    Record

    National Cheng Kung University \ Computer Science and Information Engineering \ Professor (2018 ~ now)

    Technical University of Munich \ Electronic Design Automation \ Visiting Scholar (2021 ~ 2021)

    Academia Sinica \ Institute of Information Science \ Visiting Scholar (2017 ~ 2017)

    Industrial Technology Research Institute \ Information and Communication Research Lab \ Visiting Researcher (2015 ~ 2015)

    University of California, Santa Barbara \ Electrical and Computer Engineering \ Visiting Professor (2015 ~ 2016)

    National Cheng Kung University \ Computer Science and Information Engineering \ Associate Professor (2014 ~ 2018)

    National Cheng Kung University \ Computer Sciend and Information Engineering \ Assistant Professor (2009 ~ 2014)

    Real Intent \ Timing Closure Verification \ Staff R&D Engineer (2007 ~ 2009)

    The Pennsylvania State University \ Computer Science and Engineering \ Research Assistant (2003 ~ 2007)

    Honor & Awards

    2020 CAD Contest Chair @ ICCAD

    Excellent Young Researcher Project by Ministry of Science and Technology, Taiwan (ROC)

    Research Fellowship for Experienced Researchers

    IEEE Tainan Section Best GOLD (Young Professionals) Award

    ACM Senior Member

    2015 Excellent Young Electrical Engineering

    IEEE Senior Member

    2012 Chuan Yen Research Paper Award

    2012 CAD Contest Best Advisor
    Publications

    Accepted Papers to be Published

    1. Jilan Lin, Cheng-Da Wen, Xing Hu, Tianqi Tang, Ing-Chao Lin, Yu Wang, and Yuan Xie "Rescuing RRAM-based Computing from Static and Dynamic Faults" IEEE Transactions on Computer-Aided Design on Integrated Circuits

    2. Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, and Yuan Xie "A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network" IEEE Transactions on Circuit and Systems II

    Refereed Papers

    1. Ing-Chao Lin, Da-Wei Chang, Wei-Jun Chen, Jian-Ting Ke, and Po-Han Huang "Global Clean Page First Replacement and Index Aware Multi-Stream Prefetcher in Hybrid Memory Architecture" IEEE Transactions on Computer-Aided Design on Integrated Circuits, vol. 39, no.9, pp. 1750-1763, Sept. 2020(SCI, EI)

    2. Ing-Chao Lin, Wei-Ting Chen, Yu-Cheng Chou, and Pei-Yin Chen "A Novel Comparison-Free 1D Median Filter" IEEE Transactions on Circuit and Systems II, vol. 67, no. 7, pp. 1329-1333, July 2020(SCI, EI)

    3. Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang, and Chien-Lun Lo "TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration" IEEE Transactions on Computers (TC), vol. 68, no. 12, pp. 1704-1719, 2019(SCI, EI)

    4. Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, and Sheng-Xuan Lin "Infection-Based Dead Page Prediction in Hybrid Memory Architecture" IEEE Transactions on VLSI (TVLSI) System, vol. 27, no. 10, pp. 2401-2412, 2019(SCI, EI)

    5. Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, and Wen-Zhi Huang "OCMAS: Online Page Clustering for Multi-Bank Scratchpad Memory" IEEE Trans on Computer-Aided Design on Integrated Circuits (TCAD), vol. 38, no. 2, pp. 220-233(SCI, EI)

    6. Ing-Chao Lin, Yun Kae Law, Yuan Xie "Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes" Transaction on VLSI Systems (TVLSI) , vol. 26, no. 1, pp. 50-62. 2018 (SCI, EI)

    7. Da-Wei Chang, Ing-Chao Lin*, and Lin-Chun Yong "ROHOM: Requirement-aware Online Hybrid On-chip Memory Management for Multicore Systems" IEEE Trans on Computer-Aided Design on Integrated Circuits, vol. 36, no. 3, pp. 357 - 369, 2017 (SCI, EI)

    8. Ing-Chao Lin, Yen-Han Lee, and Sheng-Wei Wang "Reducing Aging Effect on Ternary CAM" IEICE Transactions on Electronics Vol.E99-C No.7 pp.878-891, 2016 (SCI, EI)

    9. Ing-Chao Lin* and Jeng-Nian Chiou "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policies" IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 10, pp. 2149-2161, 2015 (SCI EI)

    10. Ing-Chao Lin, Yi-Ming Yang, and Cheng-Chien Lin "High-Performance Low-Power Carry Speculative Addition with Variable Latency" IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 23, no. 9, pp. 1591-1603, 2015 (SCI EI)

    11. Ing-Chao Lin*, Yu-Hung Cho, and Yi-Ming Yang "Aging-Aware Reliable Multiplier With Adaptive Hold Logic" IEEE Trans. on VLSI (TVLSI) Systems vol. 23, no. 3, pp. 544-556, March 2015 (SCI EI)

    12. Da-Wei Chang, Ing-Chao Lin*, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, and Chung-Ping Young "CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, pp. 1806-1817, Dec. 2014 (SCI EI)

    13. Kai-Chiang Wu, Ing-Chao Lin, and Yao-Te Wang "BTI-aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 10, pp.1591-1595, Oct. 2014 (SCI EI)

    14. Ing-Chao Lin*, Shun-Ming Syu, and Tsung-Yi Ho "NBTI Tolerance and Leakage Reduction using Gate Sizing" ACM Journal on Emerging Technologies in Computing Systems (JETC) , vol. 11, no. 1, pp. 1-12, Sep. 2014 (SCI EI)

    15. Ing-Chao Lin*, Kuan-Hui Li, Chia-Hao Lin, and Kai-Chiang Wu "NBTI and Leakage Reduction Using ILP-based Approach" IEEE Trans. on Very Large Scale Integration Systems (TVLSI) , vol. 22, no. 9, pp. 2034-2038, Sep. 2014 (SCI EI)

    16. Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, and Kuen-Jong Lee "Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing" IEEE Trans. on Computer-Aided Design on Integrated Circuits (TCAD), vol. 33, no. 1, pp. 127-138, Jan. 2014 (SCI EI)

    17. N. Dhanwada, R. Bergamaschi2, W. Dungan, I. Nair, P. Gramann, W. Dougherty and I.-C. Lin "Transaction-Level Modeling for Architectural and Power Analysis of PowerPC and CoreConnect based Systems" Journal of Design Automation for Embedded Systems (SCI EI)

    18. Ing-Chao Lin*, Chin-Hong Lin, and Kuan-Hui Li "Leakage and Aging Optimization Using Transmission Gate-Based Technique" IEEE Trans. on Computer-Aided Design on Integrated Circuits, vol. 32, no. 1, pp. 87-99, Jan. 2013 (SCI EI)

    Conference Papers

    International Conference

    1. Yan-Han Lee, Ing-Chao Lin, and Shen-Wei Wang "Impact of NBTI and PBTI effects on Ternary CAM" To appear in ISQED 2013 (EI)

    2. Shun-Ming Syu, Yu-Hui Shao, and Ing-Chao Lin "High-Endurance Hybrid Cache Design in CMP Architecture with Cache Partitioning and Access-Aware Policy" To appearing in GLSVLSI 2013 (EI)

    3. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang "Aging-aware Reliable Multiplier Design" Proceedings of IEEE International Conference on SoC Conference (SoCC) 2012EI

    4. Yao-Te Wang and Ing-Chao Lin "Analyzing BTI effects on retention registers" Proceedings of Asia Symposium of Quality Electronic Design (ASQED) 2012EI

    5. S.-Q. Zheng, I.-C. Lin, and Y.-H. Lee "Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect" Proceedings of Great Lakes Symposium on VLSI (GLSVLSI) 2011EI

    6. C.-H. Lin, I.-C. Lin, and K.-H. Li "TG-based technique for NBTI degradation and leakage optimization" Proceedings of International Symposium on Low Power Electronics and Design (ISLPED) 2011EI

    7. S.-Q. Zheng and I.-C. Lin "Transaction-level error susceptibility for bus-based System-on-Chip: From single-bit to multi-bit" Proc. of International Computer Symposium (ICS) 2010EI

    8. I.-C. Lin and V. Narayanan "System Level Power and Reliability Modeling" Design, Automation and Test in Europe Conference and Exhibition 2007

    9. I.-C. Lin, S. Srinivasan, V. Narayanan, N. Dhanwada "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures" Proceeding of International Symposium on Quality Electronic Design 2006

    10. I.-C. Lin and V. Narayanan "Transaction Level Power Modeling for PCI Express" TECHCON 2005

    11. N. Dhanwada, I.-C. Lin and V. Narayanan "A Power Estimation Methodology for SystemC Transaction Level Models" Proceeding of International Conference on Hardware/Software Codesign and System Synthesis 2005

    12. N. Dhanwada, R. Bergamaschi, W. Dungan, I. Nair, W. Dougherty, Y. Shin, S. Bhattacharya, I. Lin, J. Darringer, S. Paliwa "Simultaneous Exploration of Power, Physical Design and Architectural Performance Dimensions of the SoC Design Space using SEAS" IP Based SoC Design Forum & Exhibition 2004

    National Conference

    1. Yu-Hung Cho, Ing-Chao Lin, and Yi-Ming Yang "Aging-aware Reliable Multiplier Design" Proceeding of VLSI/CAD Symposium 2012

    2. Kuan-Hui Li, Ing-Chao Lin Li, and Jia-Hao Lin "NBTI Mitigation and Leakage Reduction Using ILP" Proceedings of VLSI/CAD Symposium 2012

    3. K.-H. Li, C.-H. Lin, and I.-C. Lin "TG-based Technique for NBTI Degradation and Leakage Optimization" Proceedings of VLSI/CAD Symposium 2011

    4. S.-Q. Zheng, I.-C. Lin "Mitigating NBTI using Core Rotation and Scheduled Voltage Scaling" Proc. of VLSI/CAD Symposium 2011
    Projects

    National Science Council Projects

    Project Name Since Sponsor
    Fault-Tolerant and Reconfigurable NVM-Centric Computing Architecture2021 ~ 2024Ministry of Science and Technology
    Fault-Tolerant Energy-Efficient Deep Neural Network Architecture with Nonvolatile Memory2020 ~ 2023Ministry of Science and Technology
    Fault-Tolerant Energy-Efficient Deep Neural Network Architecture with Nonvolatile Memory2020 ~ 2023Ministry of Science and Technology
    Novel Hybrid DIMM Design and Access-Aware Data Placement for Big Data Applications2017 ~ 2020Ministry of Science and Technology
    Reliable 3D Multicore System Design2014 ~ 2015Ministry of Science and Technology
    Handling Device Degradation in System-on-Chip Interconnect.2009 ~ 2010National Science Council

    General Projects

    Project Name Since Sponsor

    Students

    Students

      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)、123(Grade 1)
      123(Grade 1)

    Honor & Awards

    • IICM Outstanding Master Thesis Award
    • 2015 Taiwan IEEE Best Ph.D. Thesis Award - Honorable mention
    • 2015 National Intelligent Electronics Design Competition
    • 2014 National CAD Contest Award (陳境圃)
    • 2014 National CAD Contest Award
    • 2014 IEEE Tainan Section Best Master Thesis Award
    • 2013 Master Thesis Award (Student Yao-Te Wang)
    • 2013 IEEE Tainan Best Master Thesis Award (Yi-Hua Li)
    • 2013 Taiwan IEEE Best Master Thesis Award (Yi-Hua Li)
    • 2012 IICM Master Thesis Award
    • 2012 CAD Contest Award

    International Conference